A 7 ps Jitter 0.053 mm(2) Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shin, Dongsuk | - |
dc.contributor.author | Song, Janghoon | - |
dc.contributor.author | Chae, Hyunsoo | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.date.accessioned | 2021-09-08T13:42:30Z | - |
dc.date.available | 2021-09-08T13:42:30Z | - |
dc.date.created | 2021-06-11 | - |
dc.date.issued | 2009-09 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/119338 | - |
dc.description.abstract | This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 mu m CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7 ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm(2). | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | MIXED-MODE DLL | - |
dc.subject | DELAY | - |
dc.title | A 7 ps Jitter 0.053 mm(2) Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/JSSC.2009.2021447 | - |
dc.identifier.scopusid | 2-s2.0-70249134908 | - |
dc.identifier.wosid | 000269390700016 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.44, no.9, pp.2437 - 2451 | - |
dc.relation.isPartOf | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 44 | - |
dc.citation.number | 9 | - |
dc.citation.startPage | 2437 | - |
dc.citation.endPage | 2451 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | MIXED-MODE DLL | - |
dc.subject.keywordPlus | DELAY | - |
dc.subject.keywordAuthor | Delay-locked loop (DLL) | - |
dc.subject.keywordAuthor | duty cycle corrector (DCC) | - |
dc.subject.keywordAuthor | time-to-digital converter (TDC) | - |
dc.subject.keywordAuthor | fine code generator | - |
dc.subject.keywordAuthor | range doubler | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
(02841) 서울특별시 성북구 안암로 14502-3290-1114
COPYRIGHT © 2021 Korea University. All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.