Investigation of Simulated and Measured Program Characteristics in 4-bit/cell Charge-trap Flash (CTF) Memories

Abstract

We investigate the simulated and measured program characteristics for 4-bit program operations in silicon-oxide-nitride-oxide-silicon (SONOS) devices by using two-dimenhsional (2-D) device simulations. For this calculation, the width of the region with charge trapped locally in the drain region is assumed to be as narrow as 44 nm to remove second-bit effects during the 2-bit and 4-bit operation. We determine the reverse read voltage for screening bit-1 to be 2.5 V and confirm that both 2-bit and 4-bit; characteristics are successfully observed in our devices. From the threshold voltage shift, the densities of trapped charge, axe estimated to be 0 x 10(19), 3 x 10(19), 6 x 10(19) and 9 x 10(19) cm(-3) at 4-level states, respectively. We also find that these simulation results are reasonably consistent with the experimental results achieved in this work.