A 4-bit 2GSamples/s parallel Flash ADC using comb-type reference ladder

Abstract

This paper describes a 4 bit parallel flash Analog-to-Digital converter (ADC) using two sub Flash ADCs and comb-type reference ladder. High speed full. ash ADCs have been suffered from input referred noise which is noise itself of analog input or noise inferred from reference ladder. As power supply voltage goes lower and resolution goes higher, noise inferred from reference ladder becomes more critical to ADC's performance. The proposed ADC consists of two parallel sub-ADCs with divided reference ladder to overcome degradation due to small reference voltage step. Simulation results show that the proposed ADC achieves 3.96 effective number of bit (ENOB) for 46 MHz input signal and 3.94 ENOB for 1046 MHz input signal at 2 GHz sampling rate. At 2GSample/s, the current consumption is 45 mA including digital logic with 1.8v power supply voltage. The proposed 4 bit ADC is designed with 0.18 um CMOS technology.