Influence of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon capacitors for flash memories
DC Field | Value | Language |
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dc.contributor.author | Kim, Hee Dong | - |
dc.contributor.author | An, Ho-Myoung | - |
dc.contributor.author | Kim, Kyoung Chan | - |
dc.contributor.author | Seo, Yu Jeong | - |
dc.contributor.author | Kim, Tae Geun | - |
dc.date.accessioned | 2021-09-09T07:17:51Z | - |
dc.date.available | 2021-09-09T07:17:51Z | - |
dc.date.created | 2021-06-10 | - |
dc.date.issued | 2008-07 | - |
dc.identifier.issn | 0268-1242 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/123345 | - |
dc.description.abstract | We report the effect of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon (MONOS) capacitors. Four samples, namely as-deposited and annealed at 750, 850 and 950 degrees C for 30 s in nitrogen ambient by a rapid thermal process, were prepared and characterized for comparison. The best performance with the largest memory window of 4.4 V and the fastest program speed of 10 ms was observed for the sample annealed at 850 degrees C. In addition, the highest traps density of 6.84 x 10(18) cm(-3) was observed with ideal trap distributions for the same sample by capacitance-voltage (C-V) measurement. These results indicate that the memory traps in the ONO structure can be engineered by post-annealing to improve the electrical properties of the MONOS device. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IOP PUBLISHING LTD | - |
dc.subject | DEVICES | - |
dc.subject | CHARGE | - |
dc.subject | LAYER | - |
dc.title | Influence of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon capacitors for flash memories | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Tae Geun | - |
dc.identifier.doi | 10.1088/0268-1242/23/7/075046 | - |
dc.identifier.scopusid | 2-s2.0-47749119596 | - |
dc.identifier.wosid | 000257201100047 | - |
dc.identifier.bibliographicCitation | SEMICONDUCTOR SCIENCE AND TECHNOLOGY, v.23, no.7 | - |
dc.relation.isPartOf | SEMICONDUCTOR SCIENCE AND TECHNOLOGY | - |
dc.citation.title | SEMICONDUCTOR SCIENCE AND TECHNOLOGY | - |
dc.citation.volume | 23 | - |
dc.citation.number | 7 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Condensed Matter | - |
dc.subject.keywordPlus | DEVICES | - |
dc.subject.keywordPlus | CHARGE | - |
dc.subject.keywordPlus | LAYER | - |
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