Operation of single transistor type ferroelectric random access memory

Abstract

Verification was sought for the memory operation of a single transistor type ferroelectric random access memory (IT type FeRAM) with a circuit model for a memory cell transistor combined with a precharged capacitive decoupling sensing scheme. The wiring scheme of the IT type FeRAM array was also proposed based on the operation of the fabricated memory cell transistor. As a result, the memory operation of IT type FeRAM was confirmed at a low current level with high sensing speed and no reference cell, and the design and verification of the full chip were achieved.