Wide frequency range duty cycle correction circuit for DDR interface

Abstract

The proposed wide-range digital duty cycle correction (DCC) circuit corrects an arbitrary input clock duty ratio to 50% while preserving the output clock phase even when the input clock duty ratio suddenly changes. Also, DCC control information is preserved during power-down mode. In this work, for input frequency range of 500 MHz to 2GHz with +/- 10% duty ratio error, the output duty ratio error is corrected to be less than +/- 1.4%. The proposed DCC circuit is designed and verified using a 0.18 um CMOS technology.