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Analysis of electronic memory traps in the oxide-nitride-oxide structure of a polysilicon-oxide-nitride-oxide-semiconductor flash memory

Authors
Seo, Y. J.Kim, K. C.Kim, T. G.Sung, Y. M.Cho, H. Y.Joo, M. S.Pyi, S. H.
Issue Date
31-3월-2008
Publisher
AMER INST PHYSICS
Citation
APPLIED PHYSICS LETTERS, v.92, no.13
Indexed
SCIE
SCOPUS
Journal Title
APPLIED PHYSICS LETTERS
Volume
92
Number
13
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/123867
DOI
10.1063/1.2830000
ISSN
0003-6951
Abstract
The origin of the electron memory trap in an oxide-nitride-oxide structure deposited on n-type Si is investigated by both capacitance-voltage and deep level transient spectroscopy (DLTS). Two electron traps are observed near 0.27 and 0.54 eV, below the conduction band minimum of Si and are identified as the nitride bulk trap and the Si-SiO2 interfacial trap, respectively. The trap depth, viz., vertical distribution of the electron trap, in both nitride bulk and Si-SiO2 interface, are also estimated from the bias voltage dependent DLTS. (C) 2008 American Institute of Physics.
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공과대학 (전기전자공학부)
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