Multiple bit operation of MFISFET with Pt/SrBi2Ta2O9/Y2O3/Si gate structure
- Authors
- Il Shim, S; Kwon, YS; Kim, IS; Kim, SI; Kim, YT; Park, JH
- Issue Date
- 2004
- Publisher
- TAYLOR & FRANCIS LTD
- Keywords
- ferroelectric; MFISFET; multi-level; SBT; FRAM
- Citation
- INTEGRATED FERROELECTRICS, v.65, pp.203 - 211
- Indexed
- SCIE
SCOPUS
- Journal Title
- INTEGRATED FERROELECTRICS
- Volume
- 65
- Start Page
- 203
- End Page
- 211
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/124342
- DOI
- 10.1080/10584580490893079
- ISSN
- 1058-4587
- Abstract
- A single transistor type ferroelectric memory with multiple bit operation was presented. This cell has a metal ferroelectric insulator semiconductor field effect transistor structure. Y2O3 thin film was used as a buffer insulating layer to improve the memory characteristics and SrBi2Ta2O9 was used as a ferroelectric gate material. The multi-level characteristics of four levels with one order of drain current difference were measured according to the writing voltage step of two volt. This multi-level memory cell enables to increase the density of memory in the same space and lower the cost.
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