Inverting logic-in-memory cells comprising silicon nanowire feedback field-effect transistors
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Young-Soo | - |
dc.contributor.author | Lim, Doohyeok | - |
dc.contributor.author | Son, Jaemin | - |
dc.contributor.author | Jeon, Juhee | - |
dc.contributor.author | Cho, Kyoungah | - |
dc.contributor.author | Kim, Sangsig | - |
dc.date.accessioned | 2021-11-19T12:40:44Z | - |
dc.date.available | 2021-11-19T12:40:44Z | - |
dc.date.created | 2021-08-30 | - |
dc.date.issued | 2021-05-28 | - |
dc.identifier.issn | 0957-4484 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/127995 | - |
dc.description.abstract | In this paper, we propose inverting logic-in-memory (LIM) cells comprising silicon nanowire feedback field-effect transistors with steep switching and holding characteristics. The timing diagrams of the proposed inverting LIM cells under dynamic and static conditions are investigated via mixed-mode technology computer-aided design simulation to verify the performance. The inverting LIM cells have an operating speed of the order of nanoseconds, an ultra-high voltage gain, and a longer retention time than that of conventional dynamic random access memory. The disturbance characteristics of half-selected cells within an inverting LIM array confirm the appropriate functioning of the random access memory array. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IOP PUBLISHING LTD | - |
dc.title | Inverting logic-in-memory cells comprising silicon nanowire feedback field-effect transistors | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Sangsig | - |
dc.identifier.doi | 10.1088/1361-6528/abe894 | - |
dc.identifier.scopusid | 2-s2.0-85103492147 | - |
dc.identifier.wosid | 000626907100001 | - |
dc.identifier.bibliographicCitation | NANOTECHNOLOGY, v.32, no.22 | - |
dc.relation.isPartOf | NANOTECHNOLOGY | - |
dc.citation.title | NANOTECHNOLOGY | - |
dc.citation.volume | 32 | - |
dc.citation.number | 22 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordAuthor | silicon nanowire | - |
dc.subject.keywordAuthor | feedback field-effect transistors | - |
dc.subject.keywordAuthor | switchable memory device | - |
dc.subject.keywordAuthor | logic-in-memory | - |
dc.subject.keywordAuthor | memory hierarchy | - |
dc.subject.keywordAuthor | mixed-mode simulation | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
(02841) 서울특별시 성북구 안암로 14502-3290-1114
COPYRIGHT © 2021 Korea University. All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.