A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge
DC Field | Value | Language |
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dc.contributor.author | Lee, Kyeongho | - |
dc.contributor.author | Choi, Woong | - |
dc.contributor.author | Park, Jongsun | - |
dc.date.accessioned | 2022-02-25T20:41:31Z | - |
dc.date.available | 2022-02-25T20:41:31Z | - |
dc.date.created | 2022-02-09 | - |
dc.date.issued | 2021-08 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/136908 | - |
dc.description.abstract | This article presents an adaptive match-line (ML) discharge scheme for low-power, high-performance, and compact ternary content addressable memory (TCAM). In the proposed TCAM, the transposed cell topology enables the selectively controlled ML pull-down path and compact array area. By employing the adaptive ML discharge and ML boosting scheme, unnecessary ML discharge and redundant search-line (SL) switching are eliminated for low-cost TCAM search operation. In order to minimize ML voltage swing at a wide voltage range, a timing calibration scheme is also adopted in the proposed TCAM. A 128 x 64 test chip implemented with 65-nm CMOS technology shows that the proposed adaptive ML discharge improves up to 69% of search delay and saves 37% of search energy compared with the conventional approach at 1.1 V, 100 MHz. The measurement result shows energy efficiency of 0.6 fJ/bit/search and 8% improvement of figure-of-merit (FoM) (energy/bit/search) compared with the state-of-the-art works. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | LOW-POWER CAM | - |
dc.subject | DESIGN | - |
dc.subject | SCHEME | - |
dc.subject | NOISE | - |
dc.title | A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Jongsun | - |
dc.identifier.doi | 10.1109/JSSC.2020.3043186 | - |
dc.identifier.scopusid | 2-s2.0-85098767831 | - |
dc.identifier.wosid | 000678340400023 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.8, pp.2574 - 2584 | - |
dc.relation.isPartOf | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 56 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 2574 | - |
dc.citation.endPage | 2584 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | LOW-POWER CAM | - |
dc.subject.keywordPlus | NOISE | - |
dc.subject.keywordPlus | SCHEME | - |
dc.subject.keywordAuthor | Adaptive sensing | - |
dc.subject.keywordAuthor | content addressable memory (CAM) | - |
dc.subject.keywordAuthor | memory | - |
dc.subject.keywordAuthor | reference voltage | - |
dc.subject.keywordAuthor | sensing margin | - |
dc.subject.keywordAuthor | ternary CAM (TCAM) | - |
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