Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching
- Authors
- Konstantinou, Dimitris; Nicopoulos, Chrysostomos; Lee, Junghee; Dimitrakopoulos, Giorgos
- Issue Date
- 3월-2021
- Publisher
- ELSEVIER
- Keywords
- Micro-architecture; Multicast; Network-on-Chip; Router
- Citation
- INTEGRATION-THE VLSI JOURNAL, v.77, pp.104 - 112
- Indexed
- SCIE
SCOPUS
- Journal Title
- INTEGRATION-THE VLSI JOURNAL
- Volume
- 77
- Start Page
- 104
- End Page
- 112
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/137744
- DOI
- 10.1016/j.vlsi.2020.10.008
- ISSN
- 0167-9260
- Abstract
- Multicast on-chip communication is encountered in various cache-coherence protocols targeting multi-core processors, and its pervasiveness is increasing due to the proliferation of machine learning accelerators. Innetwork handling of multicast traffic imposes additional switching-level restrictions to guarantee deadlock freedom, while it stresses the allocation efficiency of Network-on-Chip (NoC) routers. In this work, we propose a novel partitioned NoC router microarchitecture, called SmartFork, which employs a versatile and cost-efficient multicast packet replication scheme that allows the design of high-throughput and low-cost NoCs. The design is adapted to the average branch splitting observed in real-world multicast routing algorithms. Compared to state-of-the-art NoC multicast approaches, SmartFork is demonstrated to yield high performance in terms of latency and throughput, while still offering a cost-effective implementation.
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