A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, K. | - |
dc.contributor.author | Cheon, S. | - |
dc.contributor.author | Jo, J. | - |
dc.contributor.author | Choi, W. | - |
dc.contributor.author | Park, J. | - |
dc.date.accessioned | 2022-03-05T11:41:16Z | - |
dc.date.available | 2022-03-05T11:41:16Z | - |
dc.date.created | 2022-03-02 | - |
dc.date.issued | 2021 | - |
dc.identifier.issn | 0146-7123 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/137861 | - |
dc.description.abstract | This paper presents a charge-sharing based customized 8T SRAM in-memory computing (IMC) architecture. In the proposed IMC approach, the multiply-accumulate (MAC) operation of multi-bit activations and weights is supported using the charge sharing between bit-line (BL) parasitic capacitances. The area-efficient customized 8T SRAM macro can achieve robust and voltage-scalable MAC operations due to the charge-domain computation. We also propose a split capacitor structure-based 5/6-bit reconfigurable successive approximation register analog-to-digital converter (SAR-ADC) to reduce the hardware cost of an analog readout circuit while supporting higher precision MAC operations. The proposed reconfigurable SAR-ADC has been exploited to implement layer-by-layer mixed bit-precisions in convolution layer for increasing energy efficiency with negligible accuracy loss. The 256×64 8T SRAM IMC macro has been implemented using 28nm CMOS process technology. The proposed SRAM macro achieves 11. 20-TOPS/W with a maximum clock frequency of 125MHz at 1. 0V. It also supports supply voltage scaling from 0.5V to 1.1V with the energy efficiency ranging from 8.3-TOPS/W to 35.4-TOPS/W within 1 % accuracy loss. © 2021 IEEE. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, J. | - |
dc.identifier.doi | 10.1109/DAC18074.2021.9586103 | - |
dc.identifier.scopusid | 2-s2.0-85119425447 | - |
dc.identifier.bibliographicCitation | Proceedings - Design Automation Conference, v.2021-December, pp.739 - 744 | - |
dc.relation.isPartOf | Proceedings - Design Automation Conference | - |
dc.citation.title | Proceedings - Design Automation Conference | - |
dc.citation.volume | 2021-December | - |
dc.citation.startPage | 739 | - |
dc.citation.endPage | 744 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | In-memory computing (IMC) | - |
dc.subject.keywordAuthor | bit reconfigurable SAR-ADC | - |
dc.subject.keywordAuthor | charge domain compute | - |
dc.subject.keywordAuthor | compute-in-memory (CIM) | - |
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