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A Hardware-Assisted Heartbeat Mechanism for Fault Identification in Large-Scale IoT Systems

Authors
Banerjee, MandritaBorges, CarloChoo, Kim-Kwang RaymondLee, JungheeNicopoulos, Chrysostomos
Issue Date
Mar-2022
Publisher
IEEE COMPUTER SOC
Keywords
Monitoring; Heart beat; Biomedical monitoring; Circuit faults; Logic gates; Computer security; Task analysis; Self testing; control-flow integrity; Internet-of-Things (IoT)
Citation
IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING, v.19, no.2, pp.1254 - 1265
Indexed
SCIE
SCOPUS
Journal Title
IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING
Volume
19
Number
2
Start Page
1254
End Page
1265
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/139347
DOI
10.1109/TDSC.2020.3009212
ISSN
1545-5971
Abstract
With increased inter-connectivity among disparate devices, such as Internet-of-Things (IoT) devices, including those deployed in a nation's critical infrastructure, there is a need to ensure that any failure in the deployed devices can be detected. The capability to automatically detect device failures is particularly crucial in a large-scale, complex IoT system, since it can be very time-consuming and challenging to investigate a large number of geographically-dispersed devices that are also of different makes and types. In this paper, we present a faulty-device identification technique that is designed to achieve lightweight processor-level architectural support. Specifically, a hardware-based monitoring agent is incorporated within a processor and connected to a separate monitoring program when an examination is required. By analyzing information collected by the agent, the monitoring program determines whether the device being monitored is functioning. Findings from our detailed evaluation demonstrate that the proposed approach can detect around 90 percent of the failures with minimal hardware overhead of approximately 5k gates. This area overhead is reasonable and amounts to 7.69 percent of the ARM Cortex-M4 - a lightweight IoT-class processor - that has a total area (excluding optional caches and scratch-pad memory) of 65k gates.
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