Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS With Nanosheet FET

Abstract

For the first time, by using 3-D TCAD, the advantage of using complementary FET (CI ET), which has vertically stacked nanosheet nl-ET and pFET with shared gate, is compared to standard CMOS with nanosheet FETs in perspective of CMOS inverter performance. The comparative study on CMOS operation was performed between CFET and standard CMOS in 3-nm technology node. The results indicate that, when both devices have identical DC electrical characteristics, using CI ET can increase the frequency by similar to 2.3% in iso-power and decrease power by similar to 7.3% in iso-frequency compared to the standard CMOS with separate n/pFETs while effectively reducing the area by similar to 55%. It is also investigated that such results are due to the approximately 4.5% low effective capacitance (C-eff) of the CFET compared to the standard CMOS. This low C-eff of CFET arises from the stacked structure, which causes the gate-fringe electric field overlap and short via pitch between nFET and pFET. Furthermore, the performance of CFET by different n/pFET separation distances, channel lengths, and widths are analyzed. This study can provide critical insight into the performance improvement by using CFET for sub 3-nm technology.