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A 4.5 Gb/s/pin transceiver with hybrid inter-symbol interference and far-end crosstalk equalization for next-generation high-bandwidth memory interfaceopen access

Authors
Yoon, KungryunPark, HyunsuChoi, YoonjaeSim, JincheolChoi, JonghyuckKim, Chulwoo
Issue Date
5월-2022
Publisher
WILEY
Citation
ELECTRONICS LETTERS, v.58, no.11, pp.420 - 422
Indexed
SCIE
SCOPUS
Journal Title
ELECTRONICS LETTERS
Volume
58
Number
11
Start Page
420
End Page
422
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/143080
DOI
10.1049/ell2.12494
ISSN
0013-5194
Abstract
A 4.5 Gb/s/pin transceiver capable of eliminating the inter-symbol interference (ISI) and far-end crosstalk (FEXT) in a hybrid scheme with low power and small area for next-generation high-bandwidth memory (HBM) interfaces is presented. Built around the combination of two ISI and FEXT equalization topologies, the transmitter (TX) energy efficiently reduces data-dependent jitter (DDJ) and crosstalk-induced jitter (CIJ) by using the compensation signal generated from edge detectors (ED) to ensure the sampling margin. The prototype transceiver, implemented using a 28-nm complementary metal-oxide semiconductor (CMOS) process, operates over a 3-mm mimicked silicon interposer channel with 21.2-dB loss. It achieves a data rate per density of 9 Gb/s/mu m at a bit error rate (BER) < 10(-12) with 0.23 unit interval (UI) eye width for pseudorandom binary sequence (PRBS)15 data while consuming only 1.46 pJ/bit.
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