Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages

Abstract

Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some potential challenges should be investigated. In order to reasonably predict those challenges, a TCAD (technology computer-aided design) simulation for 3D NAND structure in mass production has been run. By aggressively stacking-up and scaling-down bit cells in a string, the structure of channel hole was varied from a macaroni to nanowire. This causes the threshold voltage difference (Delta V-th) between the top cell and bottom cell in the same string. In detail, Delta V-th between the top cell and bottom cell mostly depends on the xy-scaling, but the way how Delta V-th is affected is not very dependent on the stack height.