Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology
DC Field | Value | Language |
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dc.contributor.author | Noh, Changwoo | - |
dc.contributor.author | Han, Changwoo | - |
dc.contributor.author | Won, Sang Min | - |
dc.contributor.author | Shin, Changhwan | - |
dc.date.accessioned | 2022-10-06T09:01:17Z | - |
dc.date.available | 2022-10-06T09:01:17Z | - |
dc.date.created | 2022-10-06 | - |
dc.date.issued | 2022-09 | - |
dc.identifier.issn | 2072-666X | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/144096 | - |
dc.description.abstract | In this work, we propose a vertical gate-all-around device architecture (GAA-FinFET) with the aim of simultaneously improving device performance as well as addressing the short channel effect (SCE). The GAA-FinFET was built using the technology computer-aided design (TCAD) simulation tool, and then, its electrical characteristics were quantitatively evaluated. The electrical characteristics of the GAA-FinFET were compared to those of conventional FinFET and nano-sheet FET (NSFET) at 7 nm or 5 nm nodes. When comparing the GAA-FinFET against the FinFET, it achieved not only better SCE characteristics, but also higher on-state drive current due to its gate-all-around device structure. This helps to improve the ratio of effective drive current to off-state leakage current (i.e., I-eff/I-off) by similar to 30%, resulting in an improvement in DC device performance by similar to 10%. When comparing the GAA-FinFET against the NSFET, it exhibited SCE characteristics that were comparable or superior thanks to its improved sub-channel leakage suppression. It turned out that the proposed GAA-FinFET (compared to conventional FinFET at the 7 nm or 5 nm nodes, or even beyond) is an attractive option for improving device performance in terms of SCE and series resistance. Furthermore, it is expected that the device structure of GAA-FinFET is very similar to that of conventional FinFET, resulting in further improvement to its electrical characteristics as a result of its gate-all-around device structure without significant modification with respect to the processing steps for conventional FinFET. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | MDPI | - |
dc.title | Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Shin, Changhwan | - |
dc.identifier.doi | 10.3390/mi13091551 | - |
dc.identifier.scopusid | 2-s2.0-85138731780 | - |
dc.identifier.wosid | 000858928400001 | - |
dc.identifier.bibliographicCitation | MICROMACHINES, v.13, no.9 | - |
dc.relation.isPartOf | MICROMACHINES | - |
dc.citation.title | MICROMACHINES | - |
dc.citation.volume | 13 | - |
dc.citation.number | 9 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | Y | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Chemistry | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Instruments & Instrumentation | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Chemistry, Analytical | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Instruments & Instrumentation | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | MOSFET | - |
dc.subject.keywordAuthor | nano-sheet FET | - |
dc.subject.keywordAuthor | short channel effect | - |
dc.subject.keywordAuthor | vertical gate-all-around | - |
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