Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling
DC Field | Value | Language |
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dc.contributor.author | Paik, Yoonah | - |
dc.contributor.author | Kim, Chang Hyun | - |
dc.contributor.author | Lee, Won Jun | - |
dc.contributor.author | Kim, Seon Wook | - |
dc.date.accessioned | 2022-12-12T00:40:57Z | - |
dc.date.available | 2022-12-12T00:40:57Z | - |
dc.date.created | 2022-12-08 | - |
dc.date.issued | 2022 | - |
dc.identifier.issn | 2169-3536 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/147124 | - |
dc.description.abstract | Processing-in-Memory (PIM) has been actively studied to overcome the memory bottleneck by placing computing units near or in memory, especially for efficiently processing low locality data-intensive applications. We can categorize the in-DRAM PIMs depending on how many banks perform the PIM computation by one DRAM command: per-bank and all-bank. The per-bank PIM operates only one bank, delivering low performance but preserving the standard DRAM interface and servicing non-PIM requests during PIM execution. The all-bank PIM operates all banks, achieving high performance but accompanying design issues like thermal and power consumption. We introduce the memory-computation decoupling execution to achieve the ideal all-bank PIM performance while preserving the standard JEDEC DRAM interface, i.e., performing the per-bank execution, thus easily adapted to commercial platforms. We divide the PIM execution into two phases: memory and computation phases. At the memory phase, we read the bank-private operands from a bank and store them in PIM engines' registers bank-by-bank. At the computation phase, we decouple the PIM engine from the memory array and broadcast a bank-shared operand using a standard read/write command to make all banks perform the computation simultaneously, thus reaching the computing throughput of the all-bank PIM. For extending the computation phase, i.e., maximizing all-bank execution opportunity, we introduce a compiler analysis and code generation technique to identify the bank-private and the bank-shared operands. We compared the performance of Level-2/3 BLAS, multi-batch LSTM-based Seq2Seq model, and BERT on our decoupled PIM with commercial computing platforms. In Level-3 BLAS, we achieved speedups of 75.8x , 1.2x, and 4.7x compared to CPU, GPU, and the per-bank PIM and up to 91.4% of the ideal all-bank PIM performance. Furthermore, our decoupled PIM consumed less energy than GPU and the per-bank PIM by 72.0% and 78.4%, but 7.4%, a little more than the ideal all-bank PIM. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DEEP NEURAL-NETWORKS | - |
dc.subject | ACCELERATOR | - |
dc.subject | LATENCY | - |
dc.subject | V2 | - |
dc.title | Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Seon Wook | - |
dc.identifier.doi | 10.1109/ACCESS.2022.3203051 | - |
dc.identifier.scopusid | 2-s2.0-85137583844 | - |
dc.identifier.wosid | 000873917300001 | - |
dc.identifier.bibliographicCitation | IEEE ACCESS, v.10, pp.93256 - 93272 | - |
dc.relation.isPartOf | IEEE ACCESS | - |
dc.citation.title | IEEE ACCESS | - |
dc.citation.volume | 10 | - |
dc.citation.startPage | 93256 | - |
dc.citation.endPage | 93272 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | Y | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Telecommunications | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Telecommunications | - |
dc.subject.keywordPlus | DEEP NEURAL-NETWORKS | - |
dc.subject.keywordPlus | ACCELERATOR | - |
dc.subject.keywordPlus | LATENCY | - |
dc.subject.keywordPlus | V2 | - |
dc.subject.keywordAuthor | Memory-computation decoupling | - |
dc.subject.keywordAuthor | in-memory processing | - |
dc.subject.keywordAuthor | standard memory interface | - |
dc.subject.keywordAuthor | all-bank execution | - |
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