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65-nm Si CMOS 공정 기반 123 GHz 위상동기루프 (Phase Locked Loop)
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Rieh, Jae-Sung | - |
| dc.date.accessioned | 2021-08-29T08:40:42Z | - |
| dc.date.available | 2021-08-29T08:40:42Z | - |
| dc.date.created | 2021-04-22 | - |
| dc.date.issued | 2014-09-18 | - |
| dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/38843 | - |
| dc.publisher | ieek | - |
| dc.title | 65-nm Si CMOS 공정 기반 123 GHz 위상동기루프 (Phase Locked Loop) | - |
| dc.title.alternative | 65-nm Si CMOS 공정 기반 123 GHz 위상동기루프 (Phase Locked Loop) | - |
| dc.type | Conference | - |
| dc.contributor.affiliatedAuthor | Rieh, Jae-Sung | - |
| dc.identifier.bibliographicCitation | 14th RF/Analog Circuit Workshop | - |
| dc.relation.isPartOf | 14th RF/Analog Circuit Workshop | - |
| dc.relation.isPartOf | proceeding of RF/Analog Circuit Workshop | - |
| dc.citation.title | 14th RF/Analog Circuit Workshop | - |
| dc.citation.conferencePlace | KO | - |
| dc.citation.conferenceDate | 2014-09-18 | - |
| dc.type.rims | CONF | - |
| dc.description.journalClass | 2 | - |
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