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A 1.35V-5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty cycle corrector
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | KIM, Chulwoo | - |
| dc.date.accessioned | 2021-08-29T18:45:45Z | - |
| dc.date.available | 2021-08-29T18:45:45Z | - |
| dc.date.created | 2021-04-22 | - |
| dc.date.issued | 2013-02-13 | - |
| dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/44914 | - |
| dc.publisher | IEEE | - |
| dc.title | A 1.35V-5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty cycle corrector | - |
| dc.title.alternative | A 1.35V-5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty cycle corrector | - |
| dc.type | Conference | - |
| dc.contributor.affiliatedAuthor | KIM, Chulwoo | - |
| dc.identifier.bibliographicCitation | IEEE International Solid-State Circuits Conference | - |
| dc.relation.isPartOf | IEEE International Solid-State Circuits Conference | - |
| dc.relation.isPartOf | Digest of IEEE International Solid-State Circuits Conference | - |
| dc.citation.title | IEEE International Solid-State Circuits Conference | - |
| dc.citation.conferencePlace | US | - |
| dc.citation.conferenceDate | 2014-02-09 | - |
| dc.type.rims | CONF | - |
| dc.description.journalClass | 1 | - |
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