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A 2D material-based floating gate device with linear synaptic weight update

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dc.contributor.authorPark, Eunpyo-
dc.contributor.authorKim, Minkyung-
dc.contributor.authorKim, Tae Soo-
dc.contributor.authorKim, In Soo-
dc.contributor.authorPark, Jongkil-
dc.contributor.authorKim, Jaewook-
dc.contributor.authorJeong, YeonJoo-
dc.contributor.authorLee, Suyoun-
dc.contributor.authorKim, Inho-
dc.contributor.authorPark, Jong-Keuk-
dc.contributor.authorKim, Gyu Tae-
dc.contributor.authorChang, Jiwon-
dc.contributor.authorKang, Kibum-
dc.contributor.authorKwak, Joon Young-
dc.date.accessioned2021-08-30T05:19:08Z-
dc.date.available2021-08-30T05:19:08Z-
dc.date.created2021-06-18-
dc.date.issued2020-12-28-
dc.identifier.issn2040-3364-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/50757-
dc.description.abstractNeuromorphic computing is of great interest among researchers interested in overcoming the von Neumann computing bottleneck. A synaptic device, one of the key components to realize a neuromorphic system, has a weight that indicates the strength of the connection between two neurons, and updating this weight must have linear and symmetric characteristics. Especially, a transistor-type device has a gate terminal, separating the processes of reading and updating the conductivity, used as a synaptic weight to prevent sneak path current issues during synaptic operations. In this study, we fabricate a top-gated flash memory device based on two-dimensional (2D) materials, MoS2 and graphene, as a channel and a floating gate, respectively, and Al2O3 and HfO2 to increase the tunneling efficiency. We demonstrate the linear weight updates and repeatable characteristics of applying negative/positive pulses, and also emulate spike timing-dependent plasticity (STDP), one of the learning rules in a spiking neural network (SNN).-
dc.languageEnglish-
dc.language.isoen-
dc.publisherROYAL SOC CHEMISTRY-
dc.subjectMONOLAYER MOS2-
dc.subjectMEMORY-
dc.subjectGRAPHENE-
dc.subjectARRAY-
dc.titleA 2D material-based floating gate device with linear synaptic weight update-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, Gyu Tae-
dc.identifier.doi10.1039/d0nr07403a-
dc.identifier.scopusid2-s2.0-85098916755-
dc.identifier.wosid000603084000022-
dc.identifier.bibliographicCitationNANOSCALE, v.12, no.48, pp.24503 - 24509-
dc.relation.isPartOfNANOSCALE-
dc.citation.titleNANOSCALE-
dc.citation.volume12-
dc.citation.number48-
dc.citation.startPage24503-
dc.citation.endPage24509-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaChemistry-
dc.relation.journalResearchAreaScience & Technology - Other Topics-
dc.relation.journalResearchAreaMaterials Science-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryChemistry, Multidisciplinary-
dc.relation.journalWebOfScienceCategoryNanoscience & Nanotechnology-
dc.relation.journalWebOfScienceCategoryMaterials Science, Multidisciplinary-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.subject.keywordPlusMONOLAYER MOS2-
dc.subject.keywordPlusMEMORY-
dc.subject.keywordPlusGRAPHENE-
dc.subject.keywordPlusARRAY-
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공과대학 (전기전자공학부)
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