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Rank order coding based spiking convolutional neural network architecture with energy-efficient membrane voltage updates

Authors
Tang, HoyoungCho, DonghyeonLew, DongwooKim, TaehwanPark, Jongsun
Issue Date
24-9월-2020
Publisher
ELSEVIER
Keywords
Spiking neural network; Rank order coding; Unsupervised learning; MNIST; Neuromorphic; Spike-timing dependent plasticity
Citation
NEUROCOMPUTING, v.407, pp.300 - 312
Indexed
SCIE
SCOPUS
Journal Title
NEUROCOMPUTING
Volume
407
Start Page
300
End Page
312
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/53112
DOI
10.1016/j.neucom.2020.05.031
ISSN
0925-2312
Abstract
Spiking neural network (SNN) system that uses rank order coding (ROC) as input spike encoding, gener-ally suffers from low recognition accuracy and unnecessary computations that increase complexities. In this paper, we present a Spiking convolutional neural network (Spiking CNN) architecture that signifi-cantly improves recognition accuracy as well as computation efficiencies based on a novel ROC and mod-ified kernel sizes. The proposed ROC generates spike trains based on maximum input value without sorting operations. In addition, as the recognition accuracy is affected by the reduced number of spikes as layers become deeper, the proposed ROC is inserted just before the final layer to increase the number of input spikes. The 2 x 2 pooling kernels are also replaced with 4 x 4 to reduce the network size. The hardware architecture of the proposed Spiking CNN has been implemented using 65 nm CMOS process. Neuron-centric membrane voltage update approach is also efficiently exploited in convolutional and fully connected layers to improve the hardware energy efficiencies. The Spiking CNN processor is seamlessly processing 2.85 K classifications per second with 6.79 uJ/classification. It also achieves 90.2% of recogni-tion accuracy for MNIST dataset using unsupervised learning with STDP. (C) 2020 Elsevier B.V. All rights reserved.
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공과대학 (전기전자공학부)
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