Analysis of Drain Linear Current Turn-Around Effect in Off-State Stress Mode in pMOSFET
DC Field | Value | Language |
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dc.contributor.author | Jung, Seung-Geun | - |
dc.contributor.author | Lee, Sul-Hwan | - |
dc.contributor.author | Kim, Choong-Ki | - |
dc.contributor.author | Yoo, Min-Soo | - |
dc.contributor.author | Yu, Hyun-Yong | - |
dc.date.accessioned | 2021-08-30T22:25:33Z | - |
dc.date.available | 2021-08-30T22:25:33Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2020-06 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/55544 | - |
dc.description.abstract | The turn-around effect of drain linear current (I-dlin) with stress time in a pMOSFET in the off-state stress is investigated. The degradation rate of I-dlin increases to a maximum of 6.1% at 20 s of the stress time and then continuously decreases to 3.35% at 1000 s in the off-state stress. The turn-around effect is analyzed by comparing the degradation rates of the performance parameters (I-dlin, I-dsat, SS, and V-th) in the off -state and gate induced drain leakage (gidl) -state stress modes. The results indicate that the I-dlin turn-around effect in the off-state stress, which occurs as an effect of the negative oxide charge (Q(ox)) formation, is more significant than that of the interface trap (N-it) for short stress time (before 20 s), and the donor-like N-it formation has major effects compared to those of Q(ox) over a long stress time (after 20 s). This observation shows that the stress-induced trap generation can be investigated even if the protection diode exists and critically impacts the drain current degradation and should be seriously considered in the reliability of a DRAM circuit. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DEGRADATION | - |
dc.subject | VOLTAGE | - |
dc.title | Analysis of Drain Linear Current Turn-Around Effect in Off-State Stress Mode in pMOSFET | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Yu, Hyun-Yong | - |
dc.identifier.doi | 10.1109/LED.2020.2989324 | - |
dc.identifier.scopusid | 2-s2.0-85085547312 | - |
dc.identifier.wosid | 000541155300003 | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.41, no.6, pp.804 - 807 | - |
dc.relation.isPartOf | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 41 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 804 | - |
dc.citation.endPage | 807 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | DEGRADATION | - |
dc.subject.keywordPlus | VOLTAGE | - |
dc.subject.keywordAuthor | Stress | - |
dc.subject.keywordAuthor | Degradation | - |
dc.subject.keywordAuthor | Logic gates | - |
dc.subject.keywordAuthor | MOSFET circuits | - |
dc.subject.keywordAuthor | Quality of experience | - |
dc.subject.keywordAuthor | Stress measurement | - |
dc.subject.keywordAuthor | Random access memory | - |
dc.subject.keywordAuthor | off-state stress | - |
dc.subject.keywordAuthor | gidl-state stress | - |
dc.subject.keywordAuthor | pMOSFET | - |
dc.subject.keywordAuthor | interface trap | - |
dc.subject.keywordAuthor | oxide charge trap | - |
dc.subject.keywordAuthor | turn-around effect | - |
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