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A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays With Fully Integrated 7.2-pF Total Capacitance

Authors
Maeng, JunyoungShim, MinseobJeong, JunwonPark, InhoPark, YunsooKim, Chulwoo
Issue Date
6월-2020
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Capacitively coupled level shifter (CCLS); digital low-dropout (DLDO) regulator; fully integrated voltage regulator; periodic charge refresh; power management
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.55, no.6, pp.1624 - 1636
Indexed
SCIE
SCOPUS
Journal Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume
55
Number
6
Start Page
1624
End Page
1636
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/55601
DOI
10.1109/JSSC.2019.2952132
ISSN
0018-9200
Abstract
A digital low-dropout (DLDO) regulator using p-type MOS (PMOS) and n-type MOS (NMOS) switches is proposed to achieve a sub-fs speed figure-of-merit (FoM) by reducing the total capacitance (C-TOT) and accomplishing a comparable output voltage droop (Delta V-OUT) during a load transition. The proposed DLDO uses the segmented PMOS switches to fully turn on the NMOS array, which strengthens the intrinsic NMOS loop and maintains the undershoot and overshoot voltages of 88 and 42 mV, respectively, during an 88.4-mA load transition. In addition, with the aid of the proposed voltage doubler (VD)-based periodically refreshed level shifter (PRLS), the total capacitance of DLDO to drive NMOS array is reduced to 7.2 pF, which is 3.3x smaller than that of previous work, extending the input voltage (V-IN) and load current (I-LOAD) ranges up to 0.9 V and 140 mA, respectively. The proposed DLDO is fabricated using a 28-nm CMOS process and achieves a 0.12-fs speed FoM that is 42.5x smaller than the state-of-the-art designs.
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