Ambipolar Charge Transport in Two-Dimensional WS2 Metal-Insulator-Semiconductor and Metal-Insulator-Semiconductor Field-Effect Transistors
- Authors
- Lee, Geonyeop; Oh, Sooyeoun; Kim, Janghyuk; Kim, Jihyun
- Issue Date
- 20-5월-2020
- Publisher
- AMER CHEMICAL SOC
- Keywords
- tungsten disulfide; ambipolar semiconductors; two-dimensional materials; heterostructure; metal-insulator-semiconductor field-effect transistor; enhancement mode
- Citation
- ACS APPLIED MATERIALS & INTERFACES, v.12, no.20, pp.23127 - 23133
- Indexed
- SCIE
SCOPUS
- Journal Title
- ACS APPLIED MATERIALS & INTERFACES
- Volume
- 12
- Number
- 20
- Start Page
- 23127
- End Page
- 23133
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/55663
- DOI
- 10.1021/acsami.0c04297
- ISSN
- 1944-8244
- Abstract
- Two-dimensional (2D) materials with ambipolar transport characteristics have attracted considerable attention as post-complementary metal-oxide semiconductor (CMOS) materials. These materials allow for electron- or hole-dominant conduction to be achieved in a single channel of the field-effect transistors (FETs) without an extrinsic doping. In this study, all-2D metal-insulator-semiconductor (MIS)-based devices, which were composed of all-2D graphene, hexagonal boron nitride, and WS2, exhibited ambipolar and symmetrical transport characteristics with a low surface state density (D-it,D- min approximate to 7 x 10(11) cm(-2).eV(-1)). Hole- or electron-dominant inversion under the influence of electrostatic doping was obtained in a WS2-based 2D capacitor up to a frequency range of 1 MHz. n- and p-channel conductions with enhancement-mode operations were selectively realized in a single MISFET, which presented a current on/off ratio of >10(6) and high field-effect mobility (mu(e) = 58-67 cm(2)/V.s and mu(h) = 19-30 cm(2)/V.s). Furthermore, a monolithic CMOS-like logic inverter, which employed a single WS2 flake, exhibited a high gain of 78. These results can be used to reduce the footprints of the device architectures and simplify the device fabrication processes of next-generation CMOS integrated circuits.
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