Monolithically Integrated Enhancement-Mode and Depletion-Mode beta-Ga2O3 MESFETs with Graphene-Gate Architectures and Their Logic Applications
DC Field | Value | Language |
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dc.contributor.author | Kim, Janghyuk | - |
dc.contributor.author | Kim, Jihyun | - |
dc.date.accessioned | 2021-08-31T10:16:36Z | - |
dc.date.available | 2021-08-31T10:16:36Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2020-02-12 | - |
dc.identifier.issn | 1944-8244 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/57669 | - |
dc.description.abstract | Ultrawide band gap (UWBG) beta-Ga2O3 is a promising material for next-generation power electronic devices. An enhancement-mode (E-mode) device is essential for designing power conversion systems with simplified circuitry and minimal loss. The integration of an E-mode field-effect transistor (FET) with a depletion-mode (D-mode) FET can build a high-performance logic circuit. In this study, we first demonstrated the realization of an E-mode quasi-two-dimensional (quasi-2D) beta-Ga2O3 FET with a novel graphene gate architecture via a van der Waals heterojunction. Then, we monolithically integrated it with a D-mode quasi-2D beta-Ga2O3 FET, achieving an area-efficient logic circuit. The threshold voltage of the n-channel UWBG beta-Ga2O3 material was controlled by forming a novel architecture of a double-gate graphene/beta-Ga2O3 heterojunction, where both graphene and beta-Ga2O3 were obtained by a mechanical exfoliation method. The fabricated double graphene-gate beta-Ga2O3 metal-semiconductor FET (MESFET) was operated in the E-mode with a positive threshold voltage of +0.25 V, which is approximately 1.2 V higher than that of a single-gate D-mode beta-Ga2O3 MESFET. Both E-/D-modes beta-Ga2O3 MESFETs showed excellent electrical characteristics with a subthreshold swing of 68.9 and 84.6 mV/dec, respectively, and a high on/off current ratio of approximately 10(7). A beta-Ga2O3 logic inverter composed of E-/D-mode beta-Ga2O3 devices exhibited desired inversion characteristics. The monolithic integration of an E-/D-mode quasi-2D FET with an UWBG channel layer can pave the way for various applications in smart and robust power (nano) electronics. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | AMER CHEMICAL SOC | - |
dc.subject | VOLTAGE | - |
dc.subject | TRANSISTORS | - |
dc.subject | FUTURE | - |
dc.title | Monolithically Integrated Enhancement-Mode and Depletion-Mode beta-Ga2O3 MESFETs with Graphene-Gate Architectures and Their Logic Applications | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Jihyun | - |
dc.identifier.doi | 10.1021/acsami.9b19667 | - |
dc.identifier.scopusid | 2-s2.0-85078681694 | - |
dc.identifier.wosid | 000514256400051 | - |
dc.identifier.bibliographicCitation | ACS APPLIED MATERIALS & INTERFACES, v.12, no.6, pp.7310 - 7316 | - |
dc.relation.isPartOf | ACS APPLIED MATERIALS & INTERFACES | - |
dc.citation.title | ACS APPLIED MATERIALS & INTERFACES | - |
dc.citation.volume | 12 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 7310 | - |
dc.citation.endPage | 7316 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.subject.keywordPlus | VOLTAGE | - |
dc.subject.keywordPlus | TRANSISTORS | - |
dc.subject.keywordPlus | FUTURE | - |
dc.subject.keywordAuthor | enhancement-mode FET | - |
dc.subject.keywordAuthor | depletion-mode FET | - |
dc.subject.keywordAuthor | ultrawide band gap | - |
dc.subject.keywordAuthor | two-dimensional material | - |
dc.subject.keywordAuthor | gallium oxide | - |
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