Practical Silicon-backside-protection Method for Abnormally Detection

Abstract

Nowadays, security ICs such as cryptographic modules, TPMs (Trust Platform Modules), connected car ICs, and smart card protection methods have been enhanced due to the introduction of a variety of new attack methods. Additionally, their protection mechanisms are continuously being developed and evaluated. For these reasons, attacking or hacking security chips is now more difficult than it ever has been. Nevertheless, IC failure analysis tools are being greatly improved, with many developers using them. Additionally, in using these tools, many cases involve analyzing the integrated circuit. By exploiting this analysis, attackers can perform invasive attacks [1] or hack the IC from the backside more easily than ever before. However, due to the structure of an IC, making a circuit on the back side of the silicon is more difficult than doing so on the front side. In order to resolve this issue, this paper proposes a practical silicon-backside-protection method that can protect the IC from backside attacks while minimizing its size and increasing its coverage. The proposed method uses capacitance located between the metal-layer which is unused for routing, and uses it for a passive shield (dummy shield) area.