A 9 Gb/s/ch Transceiver With Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces
- Authors
- Song, Junyoung; Kim, Yongtae; Kim, Chulwoo
- Issue Date
- 12월-2019
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Clocks; Graphics; Pins; Graphics processing units; Transceivers; Random access memory; Timing; DRAM; graphics DRAM; multi-level signaling; transceiver; memory interface; reference-less interface; data-embedded clock signaling
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.12, pp.1982 - 1986
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- Volume
- 66
- Number
- 12
- Start Page
- 1982
- End Page
- 1986
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/61411
- DOI
- 10.1109/TCSII.2019.2893498
- ISSN
- 1549-7747
- Abstract
- A 9 Gb/s/ch transceiver with a reference-less data-embedded pseudo-differential clock signaling (RDCS) for graphics memory interfaces is proposed in a 65-nm CMOS technology. In the RDCS transceiver, the output data is embedded into differential clock signal by adopting a multi-level amplitude modulation in the transmitter (TX), and the data is recovered by extracting the data information from clock signal without reference clock in the receiver (RX) side. Because the data is synchronized with the clock at the TX, the received data can be recovered without DLL in the RX side. In addition, the additional pins required in the graphics memory interfaces can be removed by applying the proposed RDCS. The proposed design achieves less than 10(-12) bit error rate with 9 Gb/s/ch data rate, and measured jitter in the recovered clock is 1.42 ps(RMS). In addition, the power efficiencies of the TX and RX are 2.33 and 1.03 pJ/bit, respectively.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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