A Parasitics-Induced Failure Mechanism for Transistors in the Bit-Line Sense Amplifier Region of DDP DDR3 DRAM During a CDM Event

Abstract

In the charged-device model (CDM) test, the peak current of the CDM is almost the same if the same package is used. Therefore, it is difficult to understand the reasons for the reduction in the CDM level of double-die package (DDP) DRAM achieved by stacking the same die and package to 30% of that of single-die package (SDP) DRAM. In this study, we analyze the CDM failure phenomenon in DDP DRAM, identify the root cause, and propose a redistribution layer (RDL) design to enhance the immunity of the CDM. To investigate the cause of the failure phenomenon, an emission test and a physical analysis were performed, and the gate oxide breakdown of a column-selection line (CSL) transistor in the sense amplifier was determined. A CDM simulation was performed after constructing a circuit in the CDM critical path to the vulnerable pin, including the CSL transistor. From the simulation results, the root cause of CDM failure was identified with the inductive peaking phenomenon due to the RDL and voltage coupling through the coupling capacitance between the RDL and CSL metal line. In other words, the voltage stress of the CSL transistor increases as the inductance and coupling capacitance increase, and the tolerable CDM immunity worsens. Moreover, no CDM failure occurs in the power and ground pins, which can be described as a low inductance of the power and ground RDL line. The reductions in the RDL inductance and the coupling capacitance of the RDL and the CSL transistor were experimentally determined for the RDL designs. As a result, the immunity of the CDM improves from 500 V to 600 and 800 V in the inductance- and coupling-capacitance-reduced designs, respectively.