Transposable 3T-SRAM Synaptic Array Using Independent Double-Gate Feedback Field-Effect Transistors
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Woo, Sola | - |
dc.contributor.author | Cho, Jinsun | - |
dc.contributor.author | Lim, Doohyeok | - |
dc.contributor.author | Cho, Kyoungah | - |
dc.contributor.author | Kim, Sangsig | - |
dc.date.accessioned | 2021-09-01T01:25:28Z | - |
dc.date.available | 2021-09-01T01:25:28Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2019-11 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/62081 | - |
dc.description.abstract | In this article, we present a transposable three-transistor static random access memory (3T-SRAM) array consisting of independent double-gate feedback field-effect transistors as binary synaptic devices and access transistors. The synaptic functions of the ${2} \times {2}$ SRAM array are investigated through mixed-mode technology computer-aided design simulations. This 3T-SRAM array provides parallel and bidirectional synaptic updates with fast operating speed. Furthermore, a simplified spike-timing-dependent plasticity learning rule is implemented by adjusting the widths of memory pulses. A compact cell area and a low-leakage power consumption allow this 3T-SRAM array to be used for adaptive synaptic devices in a large-scale neuromorphic system. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | MEMORY | - |
dc.subject | PLASTICITY | - |
dc.subject | NETWORK | - |
dc.title | Transposable 3T-SRAM Synaptic Array Using Independent Double-Gate Feedback Field-Effect Transistors | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Sangsig | - |
dc.identifier.doi | 10.1109/TED.2019.2939393 | - |
dc.identifier.scopusid | 2-s2.0-85074448151 | - |
dc.identifier.wosid | 000494419900035 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.66, no.11, pp.4753 - 4758 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.volume | 66 | - |
dc.citation.number | 11 | - |
dc.citation.startPage | 4753 | - |
dc.citation.endPage | 4758 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | MEMORY | - |
dc.subject.keywordPlus | PLASTICITY | - |
dc.subject.keywordPlus | NETWORK | - |
dc.subject.keywordAuthor | Transistors | - |
dc.subject.keywordAuthor | Logic gates | - |
dc.subject.keywordAuthor | Random access memory | - |
dc.subject.keywordAuthor | Electric potential | - |
dc.subject.keywordAuthor | Doping | - |
dc.subject.keywordAuthor | Feedback loop | - |
dc.subject.keywordAuthor | Computational modeling | - |
dc.subject.keywordAuthor | Double-gate | - |
dc.subject.keywordAuthor | feedback field-effect transistors (FBFETs) | - |
dc.subject.keywordAuthor | static random access memory (SRAM) | - |
dc.subject.keywordAuthor | synapse device | - |
dc.subject.keywordAuthor | transposable memory | - |
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