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Transposable 3T-SRAM Synaptic Array Using Independent Double-Gate Feedback Field-Effect Transistors

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dc.contributor.authorWoo, Sola-
dc.contributor.authorCho, Jinsun-
dc.contributor.authorLim, Doohyeok-
dc.contributor.authorCho, Kyoungah-
dc.contributor.authorKim, Sangsig-
dc.date.accessioned2021-09-01T01:25:28Z-
dc.date.available2021-09-01T01:25:28Z-
dc.date.created2021-06-18-
dc.date.issued2019-11-
dc.identifier.issn0018-9383-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/62081-
dc.description.abstractIn this article, we present a transposable three-transistor static random access memory (3T-SRAM) array consisting of independent double-gate feedback field-effect transistors as binary synaptic devices and access transistors. The synaptic functions of the ${2} \times {2}$ SRAM array are investigated through mixed-mode technology computer-aided design simulations. This 3T-SRAM array provides parallel and bidirectional synaptic updates with fast operating speed. Furthermore, a simplified spike-timing-dependent plasticity learning rule is implemented by adjusting the widths of memory pulses. A compact cell area and a low-leakage power consumption allow this 3T-SRAM array to be used for adaptive synaptic devices in a large-scale neuromorphic system.-
dc.languageEnglish-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectMEMORY-
dc.subjectPLASTICITY-
dc.subjectNETWORK-
dc.titleTransposable 3T-SRAM Synaptic Array Using Independent Double-Gate Feedback Field-Effect Transistors-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, Sangsig-
dc.identifier.doi10.1109/TED.2019.2939393-
dc.identifier.scopusid2-s2.0-85074448151-
dc.identifier.wosid000494419900035-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.66, no.11, pp.4753 - 4758-
dc.relation.isPartOfIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.citation.titleIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.citation.volume66-
dc.citation.number11-
dc.citation.startPage4753-
dc.citation.endPage4758-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.subject.keywordPlusMEMORY-
dc.subject.keywordPlusPLASTICITY-
dc.subject.keywordPlusNETWORK-
dc.subject.keywordAuthorTransistors-
dc.subject.keywordAuthorLogic gates-
dc.subject.keywordAuthorRandom access memory-
dc.subject.keywordAuthorElectric potential-
dc.subject.keywordAuthorDoping-
dc.subject.keywordAuthorFeedback loop-
dc.subject.keywordAuthorComputational modeling-
dc.subject.keywordAuthorDouble-gate-
dc.subject.keywordAuthorfeedback field-effect transistors (FBFETs)-
dc.subject.keywordAuthorstatic random access memory (SRAM)-
dc.subject.keywordAuthorsynapse device-
dc.subject.keywordAuthortransposable memory-
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