A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power Applications
- Authors
- Yun, Seong Jin; Lee, Jiseong; Im, Yun Chan; Kim, Yong Sin
- Issue Date
- 10월-2019
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Burst mode; digital low-dropout (DLDO) regulator; low quiescent current; self-generated temporal clock
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.27, no.10, pp.2237 - 2245
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 27
- Number
- 10
- Start Page
- 2237
- End Page
- 2245
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/62759
- DOI
- 10.1109/TVLSI.2019.2920910
- ISSN
- 1063-8210
- Abstract
- Conventional capless digital low-dropout (DLDO) regulators adopt either a high-speed clock or the burst mode at the expense of a larger quiescent current in order to overcome the degradation of the load transient response caused by the absence of an external capacitor, which causes high power consumption. In this paper, a capless DLDO regulator with a self-clocking burst logic for ultralow power applications is proposed. The self-generated clock in the burst mode of the proposed burst logic is activated temporally in order to achieve both faster load transient response and lower quiescent current. The proposed DLDO regulator is implemented in 14-nm FinFET CMOS technology. The quiescent current and figure-of-merit (FoM) of the proposed DLDO regulator are 0.69 mu A and 0.097 ps, respectively, with an active area of 0.0035 mm(2), excluding a 0.1-nF integrated output capacitor.
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