A Perspective on Test Methodologies for Supervised Machine Learning Accelerators
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Motaman, Seyedhamidreza | - |
dc.contributor.author | Ghosh, Swaroop | - |
dc.contributor.author | Park, Jongsun | - |
dc.date.accessioned | 2021-09-01T07:45:46Z | - |
dc.date.available | 2021-09-01T07:45:46Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2019-09 | - |
dc.identifier.issn | 2156-3357 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/63056 | - |
dc.description.abstract | Neural Network (NN) accelerators are essential in many emerging applications e.g., autonomous systems in making mission-critical decisions, health-care solutions to assist with diagnoses, etc. Any soft or hard failure during operation can potentially have catastrophic consequences in many of these applications. For instance, inaccurate classification during object recognition and tracking in autonomous vehicles can lead to crashes and subsequent injuries to the passengers. Therefore, testing Neural Network accelerators to ensure reliability and integrity of the underlying hardware is a crucial task to ensure the functionality, especially the ones that are used in mission-critical applications. Conventional functional, stuck-at and delay tests are not sufficient to characterize the ML systems since they face new test and validation challenges. This paper is aimed to provide a perspective on new test requirements and design for test techniques to cover ML features and detect various type of faults in NN accelerator. We discuss First-In-First-Out (FIFO) and Scratchpad based neural network hardware accelerators and propose test methods to detect the faults as well as fault location in different modules of the accelerator including MAC unit, Activation function module, and Processing Element (PE) registers. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | FAULT-TOLERANCE | - |
dc.title | A Perspective on Test Methodologies for Supervised Machine Learning Accelerators | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Jongsun | - |
dc.identifier.doi | 10.1109/JETCAS.2019.2933678 | - |
dc.identifier.wosid | 000487198700012 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, v.9, no.3, pp.562 - 569 | - |
dc.relation.isPartOf | IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS | - |
dc.citation.title | IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS | - |
dc.citation.volume | 9 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 562 | - |
dc.citation.endPage | 569 | - |
dc.type.rims | ART | - |
dc.type.docType | Article; Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | FAULT-TOLERANCE | - |
dc.subject.keywordAuthor | DFT | - |
dc.subject.keywordAuthor | stuck at fault | - |
dc.subject.keywordAuthor | neural network | - |
dc.subject.keywordAuthor | hardware accelerator | - |
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