All-2D ReS2 transistors with split gates for logic circuitry
- Authors
- Kwon, Junyoung; Shin, Yongjun; Kwon, Hyeokjae; Lee, Jae Yoon; Park, Hyunik; Watanabe, Kenji; Taniguchi, Takashi; Kim, Jihyun; Lee, Chul-Ho; Im, Seongil; Lee, Gwan-Hyoung
- Issue Date
- 17-7월-2019
- Publisher
- NATURE PUBLISHING GROUP
- Citation
- SCIENTIFIC REPORTS, v.9
- Indexed
- SCIE
SCOPUS
- Journal Title
- SCIENTIFIC REPORTS
- Volume
- 9
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/64089
- DOI
- 10.1038/s41598-019-46730-7
- ISSN
- 2045-2322
- Abstract
- Two-dimensional (2D) semiconductors, such as transition metal dichalcogenides (TMDs) and black phosphorus, are the most promising channel materials for future electronics because of their unique electrical properties. Even though a number of 2D-materials-based logic devices have been demonstrated to date, most of them are a combination of more than two unit devices. If logic devices can be realized in a single channel, it would be advantageous for higher integration and functionality. In this study we report high-performance van der Waals heterostructure (vdW) ReS2 transistors with graphene electrodes on atomically flat hBN, and demonstrate a NAND gate comprising a single ReS2 transistor with split gates. Highly sensitive electrostatic doping of ReS2 enables fabrication of gate-tunable NAND logic gates, which cannot be achieved in bulk semiconductor materials because of the absence of gate tunability. The vdW heterostructure NAND gate comprising a single transistor paves a novel way to realize "all-2D" circuitry for flexible and transparent electronic applications.
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- Appears in
Collections - College of Engineering > Department of Chemical and Biological Engineering > 1. Journal Articles
- Graduate School > KU-KIST Graduate School of Converging Science and Technology > 1. Journal Articles
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