Covered Source-Channel Tunnel Field-Effect Transistors With Trench Gate Structures
DC Field | Value | Language |
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dc.contributor.author | Woo, Sola | - |
dc.contributor.author | Kim, Sangsig | - |
dc.date.accessioned | 2021-09-01T22:54:47Z | - |
dc.date.available | 2021-09-01T22:54:47Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2019 | - |
dc.identifier.issn | 1536-125X | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/69021 | - |
dc.description.abstract | We propose a new design for covered source-channel tunnel field-effect transistors (CSC-TFETs) with trench gate structures. The I-V characteristics, ON/OFF current ratio, subthreshold swing, and band-to-band tunneling rate are analyzed using a commercial device simulator. Our proposed CSC-TFETs exhibit an ON/OFF current ratio of approximately 10(10), an ON-current of approximately 10(-5) A/mu m at room temperature, and a subthreshold swing of less than 40 mV/decade. In addition, the ON-current of the CSC-TFETs is similar to 233 times that of conventional TFETs, demonstrating that the switching characteristics are superior to those of other silicon-based TFETs. Moreover, a CSC-TFET inverter is characterized by SPICE calibration and provides a high frequency of approximately 1 GHz at a supply voltage of 1.0 V. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | STRAINED SI | - |
dc.subject | FETS | - |
dc.subject | LOGIC | - |
dc.subject | DESIGN | - |
dc.title | Covered Source-Channel Tunnel Field-Effect Transistors With Trench Gate Structures | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Sangsig | - |
dc.identifier.doi | 10.1109/TNANO.2018.2882859 | - |
dc.identifier.scopusid | 2-s2.0-85057808500 | - |
dc.identifier.wosid | 000455709300012 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.18, pp.114 - 118 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON NANOTECHNOLOGY | - |
dc.citation.title | IEEE TRANSACTIONS ON NANOTECHNOLOGY | - |
dc.citation.volume | 18 | - |
dc.citation.startPage | 114 | - |
dc.citation.endPage | 118 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | STRAINED SI | - |
dc.subject.keywordPlus | FETS | - |
dc.subject.keywordPlus | LOGIC | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordAuthor | Tunnel field-effect transistors | - |
dc.subject.keywordAuthor | TCAD simulation | - |
dc.subject.keywordAuthor | SPICE model | - |
dc.subject.keywordAuthor | covered source-channel TFET | - |
dc.subject.keywordAuthor | trench gate | - |
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