Recent Advances in FPGA Reverse Engineering
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yu, Hoyoung | - |
dc.contributor.author | Lee, Hansol | - |
dc.contributor.author | Lee, Sangil | - |
dc.contributor.author | Kim, Youngmin | - |
dc.contributor.author | Lee, Hyung-Min | - |
dc.date.accessioned | 2021-09-02T05:23:38Z | - |
dc.date.available | 2021-09-02T05:23:38Z | - |
dc.date.created | 2021-06-19 | - |
dc.date.issued | 2018-10 | - |
dc.identifier.issn | 2079-9292 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/72572 | - |
dc.description.abstract | In this paper, we review recent advances in reverse engineering with an emphasis on FPGA devices and experimentally verified advantages and limitations of reverse engineering tools. The paper first introduces essential components for programming Xilinx FPGAs (Xilinx, San Jose, CA, USA), such as Xilinx Design Language (XDL), XDL Report (XDLRC), and bitstream. Then, reverse engineering tools (Debit, BIL, and Bit2ncd), which extract the bitstream from the external memory to the FPGA and utilize it to recover the netlist, are reviewed, and their limitations are discussed. This paper also covers supplementary tools (Rapidsmith) that can adjust the FPGA design flow to support reverse engineering. Finally, reverse engineering projects for non-Xilinx products, such as Lattice FPGAs (Icestorm) and Altera FPGAs (QUIP), are introduced to compare the reverse engineering capabilities by various commercial FPGA products. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | MDPI | - |
dc.title | Recent Advances in FPGA Reverse Engineering | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Lee, Hyung-Min | - |
dc.identifier.doi | 10.3390/electronics7100246 | - |
dc.identifier.scopusid | 2-s2.0-85056249297 | - |
dc.identifier.wosid | 000448544900038 | - |
dc.identifier.bibliographicCitation | ELECTRONICS, v.7, no.10 | - |
dc.relation.isPartOf | ELECTRONICS | - |
dc.citation.title | ELECTRONICS | - |
dc.citation.volume | 7 | - |
dc.citation.number | 10 | - |
dc.type.rims | ART | - |
dc.type.docType | Review | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordAuthor | reverse engineering | - |
dc.subject.keywordAuthor | FPGA | - |
dc.subject.keywordAuthor | hardware security | - |
dc.subject.keywordAuthor | bitstream | - |
dc.subject.keywordAuthor | netlists | - |
dc.subject.keywordAuthor | Xilinx | - |
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