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Series resistance in different operation regime of junctionless transistors
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Jeon, Dae-Young | - |
| dc.contributor.author | Park, So Jeong | - |
| dc.contributor.author | Mouis, Mireille | - |
| dc.contributor.author | Barraud, Sylvain | - |
| dc.contributor.author | Kim, Gyu-Tae | - |
| dc.contributor.author | Ghibaudo, Gerard | - |
| dc.date.accessioned | 2021-09-02T13:56:46Z | - |
| dc.date.available | 2021-09-02T13:56:46Z | - |
| dc.date.created | 2021-06-16 | - |
| dc.date.issued | 2018-03 | - |
| dc.identifier.issn | 0038-1101 | - |
| dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/76796 | - |
| dc.description.abstract | Operation mode dependent series resistance (R-sd) behavior of junctionless transistors (JLTs) has been discussed in detail. R-sd was increased for decreasing gate bias in bulk conduction regime, while a constant value of R-sd was found in accumulation operation mode. Those results were compared to conventional inversion-mode (IM) transistors, verified by 2D numerical simulation and temperature dependence of extracted R-sd. This work provides key information for a better understanding of JLT operation affected by R-sd effects with different state of conduction channel. | - |
| dc.language | English | - |
| dc.language.iso | en | - |
| dc.publisher | PERGAMON-ELSEVIER SCIENCE LTD | - |
| dc.subject | NANOWIRE TRANSISTORS | - |
| dc.subject | PARAMETER EXTRACTION | - |
| dc.title | Series resistance in different operation regime of junctionless transistors | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Kim, Gyu-Tae | - |
| dc.identifier.doi | 10.1016/j.sse.2017.12.013 | - |
| dc.identifier.wosid | 000425491200014 | - |
| dc.identifier.bibliographicCitation | SOLID-STATE ELECTRONICS, v.141, pp.92 - 95 | - |
| dc.relation.isPartOf | SOLID-STATE ELECTRONICS | - |
| dc.citation.title | SOLID-STATE ELECTRONICS | - |
| dc.citation.volume | 141 | - |
| dc.citation.startPage | 92 | - |
| dc.citation.endPage | 95 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Article | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalResearchArea | Physics | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
| dc.relation.journalWebOfScienceCategory | Physics, Condensed Matter | - |
| dc.subject.keywordPlus | NANOWIRE TRANSISTORS | - |
| dc.subject.keywordPlus | PARAMETER EXTRACTION | - |
| dc.subject.keywordAuthor | Junctionless transistors (JLTs) | - |
| dc.subject.keywordAuthor | Series resistance (R-sd) | - |
| dc.subject.keywordAuthor | Bulk channel | - |
| dc.subject.keywordAuthor | Accumulation channel | - |
| dc.subject.keywordAuthor | Numerical simulation and temperature dependence | - |
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Related Researcher
- Kim, Gyu Tae
- College of Engineering (School of Electrical Engineering)