Reconfigurable Si Nanowire Nonvolatile Transistors
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, So Jeong | - |
dc.contributor.author | Jeon, Dae-Young | - |
dc.contributor.author | Piontek, Sabrina | - |
dc.contributor.author | Grube, Matthias | - |
dc.contributor.author | Ocker, Johannes | - |
dc.contributor.author | Sessi, Violetta | - |
dc.contributor.author | Heinzig, Andre | - |
dc.contributor.author | Trommer, Jens | - |
dc.contributor.author | Kim, Gyu-Tae | - |
dc.contributor.author | Mikolajick, Thomas | - |
dc.contributor.author | Weber, Walter M. | - |
dc.date.accessioned | 2021-09-02T17:17:01Z | - |
dc.date.available | 2021-09-02T17:17:01Z | - |
dc.date.created | 2021-06-16 | - |
dc.date.issued | 2018-01 | - |
dc.identifier.issn | 2199-160X | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/78551 | - |
dc.description.abstract | Reconfigurable transistors merge unipolar p- and n-type characteristics of field-effect transistors into a single programmable device. Combinational circuits have shown benefits in area and power consumption by fine-grain reconfiguration of complete logic blocks at runtime. To complement this volatile programming technology, a proof of concept for individually addressable reconfigurable nonvolatile transistors is presented. A charge-trapping stack is incorporated, and four distinct and stable states in a single device are demonstrated. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | WILEY | - |
dc.subject | SILICON NANOWIRE | - |
dc.subject | SONOS MEMORY | - |
dc.subject | BARRIER | - |
dc.title | Reconfigurable Si Nanowire Nonvolatile Transistors | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, So Jeong | - |
dc.contributor.affiliatedAuthor | Kim, Gyu-Tae | - |
dc.identifier.doi | 10.1002/aelm.201700399 | - |
dc.identifier.scopusid | 2-s2.0-85038089904 | - |
dc.identifier.wosid | 000419670400019 | - |
dc.identifier.bibliographicCitation | ADVANCED ELECTRONIC MATERIALS, v.4, no.1 | - |
dc.relation.isPartOf | ADVANCED ELECTRONIC MATERIALS | - |
dc.citation.title | ADVANCED ELECTRONIC MATERIALS | - |
dc.citation.volume | 4 | - |
dc.citation.number | 1 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | SILICON NANOWIRE | - |
dc.subject.keywordPlus | SONOS MEMORY | - |
dc.subject.keywordPlus | BARRIER | - |
dc.subject.keywordAuthor | intrinsic silicon nanowires | - |
dc.subject.keywordAuthor | nonvolatile transistors | - |
dc.subject.keywordAuthor | reconfigurable field effect transistors | - |
dc.subject.keywordAuthor | reconfigurable memory | - |
dc.subject.keywordAuthor | Schottky barrier | - |
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