Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions
DC Field | Value | Language |
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dc.contributor.author | Park, Byeonggil | - |
dc.contributor.author | Park, Jongsun | - |
dc.contributor.author | Lee, Youngjoo | - |
dc.date.accessioned | 2021-09-02T21:12:53Z | - |
dc.date.available | 2021-09-02T21:12:53Z | - |
dc.date.created | 2021-06-16 | - |
dc.date.issued | 2018 | - |
dc.identifier.issn | 2169-3536 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/80929 | - |
dc.description.abstract | Recently, there are increasing demands for fully flexible Bose Chaudhuri Hocquenghem (BCH) decoders, which can support different dimensions of Galois fields (GF) operations. As the previous BCH decoders are mainly targeting the fixed GF operations, the conventional techniques are no longer suitable for multiple GF dimensions. For the area-optimized flexible BCH decoders, in this paper, we present several optimization schemes for reducing hardware costs of multi-dimensional GF operations. In the proposed optimizations, we first reformulate the matrix operations in syndrome calculation and Chien search for sharing more common sub-expressions between GF operations having different dimensions. The cell based multi-m GF multiplier is newly introduced for the area-efficient flexible key-equation solver. As case studies, we design several prototype flexible BCH decoders for digital video broadcasting systems and NAND flash memory controllers managing different page sizes. The implementation results show that the proposed fully-flexible BCH decoder architecture remarkably enhances the area-efficiency compared with the conventional solutions. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | HIGH-THROUGHPUT | - |
dc.subject | ALGORITHMS | - |
dc.subject | DESIGN | - |
dc.subject | MEMORY | - |
dc.subject | CODES | - |
dc.subject | ECC | - |
dc.title | Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Jongsun | - |
dc.identifier.doi | 10.1109/ACCESS.2018.2815640 | - |
dc.identifier.scopusid | 2-s2.0-85043781719 | - |
dc.identifier.wosid | 000428956400001 | - |
dc.identifier.bibliographicCitation | IEEE ACCESS, v.6, pp.14498 - 14509 | - |
dc.relation.isPartOf | IEEE ACCESS | - |
dc.citation.title | IEEE ACCESS | - |
dc.citation.volume | 6 | - |
dc.citation.startPage | 14498 | - |
dc.citation.endPage | 14509 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Telecommunications | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Telecommunications | - |
dc.subject.keywordPlus | HIGH-THROUGHPUT | - |
dc.subject.keywordPlus | ALGORITHMS | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | MEMORY | - |
dc.subject.keywordPlus | CODES | - |
dc.subject.keywordPlus | ECC | - |
dc.subject.keywordAuthor | Bose-Chaudhuri-Hocquenghem (BCH) decoder | - |
dc.subject.keywordAuthor | Galois-field (GF) arithmetic | - |
dc.subject.keywordAuthor | optimization | - |
dc.subject.keywordAuthor | low complexity | - |
dc.subject.keywordAuthor | VLSI design | - |
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