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Adaptive ECC for Tailored Protection of Nanoscale Memory

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dc.contributor.authorShin, Dongyeob-
dc.contributor.authorPark, Jongsun-
dc.contributor.authorPark, Jangwon-
dc.contributor.authorPaul, Somnath-
dc.contributor.authorBhunia, Swarup-
dc.date.accessioned2021-09-02T23:55:14Z-
dc.date.available2021-09-02T23:55:14Z-
dc.date.created2021-06-19-
dc.date.issued2017-11-
dc.identifier.issn2168-2356-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/81805-
dc.languageEnglish-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectRELIABILITY-
dc.subjectCIRCUITS-
dc.titleAdaptive ECC for Tailored Protection of Nanoscale Memory-
dc.typeArticle-
dc.contributor.affiliatedAuthorPark, Jongsun-
dc.identifier.doi10.1109/MDAT.2016.2615844-
dc.identifier.scopusid2-s2.0-85037732215-
dc.identifier.wosid000416261800010-
dc.identifier.bibliographicCitationIEEE DESIGN & TEST, v.34, no.6, pp.84 - 93-
dc.relation.isPartOfIEEE DESIGN & TEST-
dc.citation.titleIEEE DESIGN & TEST-
dc.citation.volume34-
dc.citation.number6-
dc.citation.startPage84-
dc.citation.endPage93-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusRELIABILITY-
dc.subject.keywordPlusCIRCUITS-
dc.subject.keywordAuthorError Correction Code (ECC)-
dc.subject.keywordAuthorMemory Failures-
dc.subject.keywordAuthorRobust Nanoscale Memory-
dc.subject.keywordAuthorRun-time Protection-
dc.subject.keywordAuthorVariable ECC-
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