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A decoupled bit shifting technique using data encoding/decoding for DRAM redundancy repair

Authors
Choi, Kyu HyunJun, JaeYungKim, HokwonKim, Seon WookHan, Youngsun
Issue Date
10-7월-2017
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Keywords
bit shifting; redundancy repair; encoding; decoding; DRAM
Citation
IEICE ELECTRONICS EXPRESS, v.14, no.13
Indexed
SCIE
SCOPUS
Journal Title
IEICE ELECTRONICS EXPRESS
Volume
14
Number
13
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/82845
DOI
10.1587/elex.14.20170385
ISSN
1349-2543
Abstract
Redundancy repairs are commonly used to support fault tolerance in DRAM systems and recently, the processor performance has been greatly improved, so DRAM access latency has become an important issue. However, existing redundancy repairs using shift logic have difficulty in further reducing the latency due to their design limitations. In this paper, we propose a novel, decoupled bit shifting technique that uses data encoding and decoding to resolve this limitation. Our technique decouples the conventional shifting logic into two units, a bit selection vector generator (BSVG) and a data manipulation unit (DMU), to reduce the latency overhead of the shifting logic. Our technique can apply the BSVG in parallel with other logic consuming long latency operations, thereby reducing the total latency compared to conventional shifting logic. We implement both serial and parallel approaches to demonstrate that the parallel approach performs significantly better than the serial one in terms of delay, area, and dynamic power consumption. The experimental results show that our bit shifting technique is applicable for redundancy repair technique in state-of-the-art DRAM architectures.
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