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Investigation of the layout and optical proximity correction effects to control the trench etching process on 4H-SiC

Authors
Kyoung, SinsuJung, Eun-SikSung, Man Young
Issue Date
7월-2017
Publisher
KOREAN INST METALS MATERIALS
Keywords
area effect; micro-trench; 4H-SiC trench etching; loading effect; RIE lagging; OPC
Citation
ELECTRONIC MATERIALS LETTERS, v.13, no.4, pp.368 - 372
Indexed
SCIE
SCOPUS
KCI
Journal Title
ELECTRONIC MATERIALS LETTERS
Volume
13
Number
4
Start Page
368
End Page
372
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/82885
DOI
10.1007/s13391-017-1721-z
ISSN
1738-8090
Abstract
Although trench gate and super-junction technology have micro-trench problems when applied to the SiC process due to the material characteristics. In this paper, area effects are analyzed from the test element group with various patterns and optical proximity correction (OPC) methods are proposed and analyzed to reduce micro-trenches in the SiC trench etching process. First, the loading effects were analyzed from pattern samples with various trench widths (W-t). From experiments, the area must limited under a proper size for a uniform etching profile and reduced micro-trenches because a wider area accelerates the etch rate. Second, the area effects were more severely unbalanced at corner patterns because the corner pattern necessarily has an in-corner and out-corner that have different etching areas to each other. We can balance areas using OPC patterns to overcome this. Experiments with OPC represented improved micro-trench profile from when comparing differences of trench depth (Delta d(t)) at out corner and in corner. As a result, the area effects can be used to improve the trench profile with optimized etching process conditions. Therefore, the trench gate and super-junction pillar of the SiC power MOSFET can have an improved uniform profile without micro-trenches using proper design and OPC.
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