A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier
DC Field | Value | Language |
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dc.contributor.author | Kim, Ja-Young | - |
dc.contributor.author | Song, Junyoung | - |
dc.contributor.author | You, Jungtaek | - |
dc.contributor.author | Hwang, Sewook | - |
dc.contributor.author | Bae, Sang-Geun | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.date.accessioned | 2021-09-03T05:34:38Z | - |
dc.date.available | 2021-09-03T05:34:38Z | - |
dc.date.created | 2021-06-16 | - |
dc.date.issued | 2017-06 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/83279 | - |
dc.description.abstract | This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6-GHz clock with low jitter. In addition, the voltage-controlled oscillator operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56-ps rms jitter, consumes 13.2 mW at 6 Gb/s, and occupies 0.0944 mm(2) in a 65-nm CMOS technology. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/TCSII.2015.2503721 | - |
dc.identifier.scopusid | 2-s2.0-85027587884 | - |
dc.identifier.wosid | 000402731000010 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.6, pp.650 - 654 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.volume | 64 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 650 | - |
dc.citation.endPage | 654 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | Clock and data recovery circuit (CDR) | - |
dc.subject.keywordAuthor | clock frequency multiplier | - |
dc.subject.keywordAuthor | referenceless | - |
dc.subject.keywordAuthor | referenceless frequency acquisition circuit (RFAC) | - |
dc.subject.keywordAuthor | single loop | - |
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