A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier
- Authors
- Kim, Ja-Young; Song, Junyoung; You, Jungtaek; Hwang, Sewook; Bae, Sang-Geun; Kim, Chulwoo
- Issue Date
- 6월-2017
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Clock and data recovery circuit (CDR); clock frequency multiplier; referenceless; referenceless frequency acquisition circuit (RFAC); single loop
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.6, pp.650 - 654
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- Volume
- 64
- Number
- 6
- Start Page
- 650
- End Page
- 654
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/83279
- DOI
- 10.1109/TCSII.2015.2503721
- ISSN
- 1549-7747
- Abstract
- This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6-GHz clock with low jitter. In addition, the voltage-controlled oscillator operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56-ps rms jitter, consumes 13.2 mW at 6 Gb/s, and occupies 0.0944 mm(2) in a 65-nm CMOS technology.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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