A Return-to-zero DAC with Tri-state Switching Scheme for Multiple Nyquist Operations
- Authors
- Yun, Jaecheol; Jung, Yun-Hwan; Yoo, Taegeun; Hong, Yohan; Kim, Ju Eon; Yoon, Dong-Hyun; Lee, Sung-Min; Jo, Youngkwon; Kim, Yong Sin; Baek, Kwang-Hyun
- Issue Date
- 6월-2017
- Publisher
- IEEK PUBLICATION CENTER
- Keywords
- Return-to-zero (RZ); digital-to-analog converter (DAC); tri-state switching scheme
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.17, no.3, pp.378 - 386
- Indexed
- SCIE
SCOPUS
KCI
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 17
- Number
- 3
- Start Page
- 378
- End Page
- 386
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/83346
- DOI
- 10.5573/JSTS.2017.17.3.378
- ISSN
- 1598-1657
- Abstract
- A return-to-zero (RZ) digital-to-analog converter (DAC) with a tri-state switching scheme is proposed in this paper. The proposed scheme provides a triple weight output for RZ operation by using a conventional differential current switch and simple pseudo-differential F/Fs. The RZ function is realized with only two additional transistors in each F/F cell, which results in a power dissipation increase of less than 5%. To verify the performance of the proposed method, a 10-bit RZ DAC is fabricated using standard 180-nm CMOS technology. Measured results show that the worst SFDR performances are 60 dBc and 55 dBc in the 1st and 2nd Nyquist bands, respectively, when operating at 650 MHz clock frequency. The total power consumption is 64 mW, and the active area occupies 0.25 mm(2).
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- Appears in
Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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