CMOS 120 GHz Phase-Locked Loops Based on Two Different VCO Topologies
DC Field | Value | Language |
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dc.contributor.author | Yoo, Junghwan | - |
dc.contributor.author | Rieh, Jae-Sung | - |
dc.date.accessioned | 2021-09-03T08:06:54Z | - |
dc.date.available | 2021-09-03T08:06:54Z | - |
dc.date.created | 2021-06-16 | - |
dc.date.issued | 2017-04 | - |
dc.identifier.issn | 2234-8409 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/84064 | - |
dc.description.abstract | This work describes the development and comparison of two phase-locked loops (PLLs) based on a 65-nm CMOS technology. The PLLs incorporate two different topologies for the output voltage-controlled oscillator (VCO): LC cross-coupled and differential Colpitts. The measured locking ranges of the LC cross-coupled VCO-based phase-locked loop (PLL1) and the Colpitts VCO-based phase-locked loop (PLL2) are 119.84-122.61 GHz and 126.53-129.29 GHz, respectively. Th e output powers of PLL1 and PLL2 are - 8.6 dBm and -10.5 dBm with DC power consumptions of 127.3 mW and 142.8 mW, respectively. The measured phase noise of PLL1 is -59.2 at 10 kHz offset and -104.5 at 10 MHz offset, and the phase noise of PLL2 is -60.9 dBc/ Hz at 10 kHz offset and -104.4 dBc/Hz at 10 MHz offset. The chip sizes are 1,080 mu m x 760 mu m (PLL1) and 1,100 mu m x 800 mu m (PLL2), including the probing pads. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | KOREAN INST ELECTROMAGNETIC ENGINEERING & SCIENCE | - |
dc.title | CMOS 120 GHz Phase-Locked Loops Based on Two Different VCO Topologies | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Rieh, Jae-Sung | - |
dc.identifier.doi | 10.5515/JKIEES.2017.17.2.98 | - |
dc.identifier.scopusid | 2-s2.0-85018970981 | - |
dc.identifier.wosid | 000411612200008 | - |
dc.identifier.bibliographicCitation | JOURNAL OF ELECTROMAGNETIC ENGINEERING AND SCIENCE, v.17, no.2, pp.98 - 104 | - |
dc.relation.isPartOf | JOURNAL OF ELECTROMAGNETIC ENGINEERING AND SCIENCE | - |
dc.citation.title | JOURNAL OF ELECTROMAGNETIC ENGINEERING AND SCIENCE | - |
dc.citation.volume | 17 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 98 | - |
dc.citation.endPage | 104 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.identifier.kciid | ART002220760 | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | CMOS | - |
dc.subject.keywordAuthor | Frequency Doubler | - |
dc.subject.keywordAuthor | Phase-Locked Loop (PLL) | - |
dc.subject.keywordAuthor | Signal Source | - |
dc.subject.keywordAuthor | Voltage-Controlled Oscillator (VCO) | - |
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