Towards refresh-optimized EDRAM-based caches with a selective fine-grain round-robin refresh scheme
DC Field | Value | Language |
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dc.contributor.author | Kong, Joonho | - |
dc.contributor.author | Gong, Young-Ho | - |
dc.contributor.author | Chung, Sung Woo | - |
dc.date.accessioned | 2021-09-03T09:15:43Z | - |
dc.date.available | 2021-09-03T09:15:43Z | - |
dc.date.created | 2021-06-16 | - |
dc.date.issued | 2017-03 | - |
dc.identifier.issn | 0141-9331 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/84376 | - |
dc.description.abstract | Recently, EDRAM cells have gained much attention as a promising alternative to construct on-chip memories. However, due to inherent characteristics of DRAM cells, they need to be refreshed periodically, causing a huge refresh energy burden. Particularly, employing EDRAM cells in large-scale last-level caches will make refresh burden much higher due to their large capacity. In this paper, we propose a selective fine-grain round-robin refresh scheme for both performance improvement and refresh energy reduction. To reduce bank conflicts between normal cache accesses and refresh operations, we employ a refresh scheme which refreshes cache lines in a bank-wise round-robin fashion. We also apply a selective refresh depending on the inclusive information in cache hierarchies. For the data which reside in both LLC and upper-level cache (i.e., L2 cache), the data access will be filtered by' the upper-level cache. Based on this insight, we skip the refresh to the cache block in the EDRAM-based LLC which also exists in the upper-level caches. By doing so, we can reduce unnecessary refresh operations in EDRAM-based LLCs. According to our evaluation, our proposed scheme improves performance by 7.3% and reduces energy per instruction by 13.3% compared to the baseline all-bank refresh scheme. (C) 2016 Elsevier B.V. All rights reserved. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | ELSEVIER SCIENCE BV | - |
dc.subject | ENERGY | - |
dc.subject | POWER | - |
dc.title | Towards refresh-optimized EDRAM-based caches with a selective fine-grain round-robin refresh scheme | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Chung, Sung Woo | - |
dc.identifier.doi | 10.1016/j.micpro.2016.11.007 | - |
dc.identifier.scopusid | 2-s2.0-85006837042 | - |
dc.identifier.wosid | 000395598300010 | - |
dc.identifier.bibliographicCitation | MICROPROCESSORS AND MICROSYSTEMS, v.49, pp.95 - 104 | - |
dc.relation.isPartOf | MICROPROCESSORS AND MICROSYSTEMS | - |
dc.citation.title | MICROPROCESSORS AND MICROSYSTEMS | - |
dc.citation.volume | 49 | - |
dc.citation.startPage | 95 | - |
dc.citation.endPage | 104 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | ENERGY | - |
dc.subject.keywordPlus | POWER | - |
dc.subject.keywordAuthor | Embedded dynamic random access Memory | - |
dc.subject.keywordAuthor | Refresh | - |
dc.subject.keywordAuthor | Last-level cache | - |
dc.subject.keywordAuthor | Performance | - |
dc.subject.keywordAuthor | Energy-efficiency | - |
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