A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique
DC Field | Value | Language |
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dc.contributor.author | Song, Junyoung | - |
dc.contributor.author | Lee, Hyun-Woo | - |
dc.contributor.author | Hwang, Sewook | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.date.accessioned | 2021-09-03T11:14:23Z | - |
dc.date.available | 2021-09-03T11:14:23Z | - |
dc.date.created | 2021-06-16 | - |
dc.date.issued | 2017-01 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/84993 | - |
dc.description.abstract | A 10 Gbits/s/pin graphics DRAM interface is developed in 65-nm CMOS technology. Several design techniques are proposed for high-speed operation in a noisy environment. A fast precharging data sampler guarantees high-speed sampling without the need for a decision feedback equalizer. In order to increase the data sampling margin, the PLL bandwidth is optimized depending on the system noises, which reduces the clock jitter by up to 55.1%. The crosstalk-induced jitter (CIJ) reduction technique suppresses the DQs jitter by employing the suggested training sequence for the GDDR5 interface. Pre- and de-emphasis are merged in one auxiliary driver. This chip operates at 10 Gbits/s/pin and exhibits a data eye opening of 0.78 UI with the CIJ reduction technique. The power consumptions of the TX and RX are 8.28 and 5.5 pJ/b/channel, respectively. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | SILICON | - |
dc.title | A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/TVLSI.2016.2580713 | - |
dc.identifier.scopusid | 2-s2.0-84978823986 | - |
dc.identifier.wosid | 000394591600028 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.1, pp.344 - 353 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 25 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 344 | - |
dc.citation.endPage | 353 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | SILICON | - |
dc.subject.keywordAuthor | Adaptive-bandwidth PLL | - |
dc.subject.keywordAuthor | crosstalk-induced jitter (CIJ) reduction | - |
dc.subject.keywordAuthor | fast precharging sampler (FP-sampler) | - |
dc.subject.keywordAuthor | graphics DRAM interface | - |
dc.subject.keywordAuthor | intersymbol interference (ISI) reduction | - |
dc.subject.keywordAuthor | pre-and de-emphasis | - |
dc.subject.keywordAuthor | receiver | - |
dc.subject.keywordAuthor | training sequence | - |
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