A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique
- Authors
- Song, Junyoung; Lee, Hyun-Woo; Hwang, Sewook; Kim, Chulwoo
- Issue Date
- 1월-2017
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Adaptive-bandwidth PLL; crosstalk-induced jitter (CIJ) reduction; fast precharging sampler (FP-sampler); graphics DRAM interface; intersymbol interference (ISI) reduction; pre-and de-emphasis; receiver; training sequence
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.1, pp.344 - 353
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 25
- Number
- 1
- Start Page
- 344
- End Page
- 353
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/84993
- DOI
- 10.1109/TVLSI.2016.2580713
- ISSN
- 1063-8210
- Abstract
- A 10 Gbits/s/pin graphics DRAM interface is developed in 65-nm CMOS technology. Several design techniques are proposed for high-speed operation in a noisy environment. A fast precharging data sampler guarantees high-speed sampling without the need for a decision feedback equalizer. In order to increase the data sampling margin, the PLL bandwidth is optimized depending on the system noises, which reduces the clock jitter by up to 55.1%. The crosstalk-induced jitter (CIJ) reduction technique suppresses the DQs jitter by employing the suggested training sequence for the GDDR5 interface. Pre- and de-emphasis are merged in one auxiliary driver. This chip operates at 10 Gbits/s/pin and exhibits a data eye opening of 0.78 UI with the CIJ reduction technique. The power consumptions of the TX and RX are 8.28 and 5.5 pJ/b/channel, respectively.
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