Random Dopant Fluctuation-Induced Threshold Voltage Variation-Immune Ge FinFET With Metal-Interlayer-Semiconductor Source/Drain

Abstract

The impact of process-induced random dopant fluctuation (RDF)-induced threshold voltage (Vth) variation on the performance of 7-nm n-type germanium (Ge) FinFETs with and without a metal-interlayer-semiconductor (MIS) source/drain (S/D) structure is investigated using 3-D TCAD simulations. In order to reduce the RDF-induced Vth variation, an MIS S/D structure with a heavily doped n-type zinc oxide (ZnO) interlayer is used in the S/D region of the Ge FinFET. Thus, without performance degradation, the Ge FinFET with an MIS S/D structure achieves approximately threefold reduction in the RDF-induced Vth variation (versus without an MIS S/D structure). The impact of various fin parameters (i. e., fin height and fin width) on the RDF-induced Vth variation is also investigated. It is noteworthy that variation is suppressed as the fin height (fin width) increases (decreases).