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Analytical Model of the Parasitic Bipolar Junction Transistor in Low-Doped Double-Gate FinFETs for Pass-Gate Circuits
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yi, Boram | - |
| dc.contributor.author | Lee, Chang-Yong | - |
| dc.contributor.author | Oh, Jin-Hwan | - |
| dc.contributor.author | Lee, Boung Jun | - |
| dc.contributor.author | Seo, Sungkyu | - |
| dc.contributor.author | Yang, Ji-Woon | - |
| dc.date.accessioned | 2021-09-03T18:59:51Z | - |
| dc.date.available | 2021-09-03T18:59:51Z | - |
| dc.date.created | 2021-06-16 | - |
| dc.date.issued | 2016-10 | - |
| dc.identifier.issn | 0018-9383 | - |
| dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/87241 | - |
| dc.description.abstract | The transient parasitic bipolar effect in floating-body double-gate FinFETs with low-doped bodies is analytically modeled. The obtained analytical transient bipolar current and charge models have predictive power for various device structures. These models are applicable when the majority carrier concentration in accumulation conditions noticeably exceeds the body doping concentration. The physical insights obtained from the developed current model are used to analyze the transient bipolar current I-BJT(t) for different device structures. It is shown that the gate-body-source capacitive coupling is an important parameter in I-BJT(t) control. | - |
| dc.language | English | - |
| dc.language.iso | en | - |
| dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
| dc.subject | SOI MOSFETS | - |
| dc.subject | DG MOSFETS | - |
| dc.title | Analytical Model of the Parasitic Bipolar Junction Transistor in Low-Doped Double-Gate FinFETs for Pass-Gate Circuits | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Seo, Sungkyu | - |
| dc.contributor.affiliatedAuthor | Yang, Ji-Woon | - |
| dc.identifier.doi | 10.1109/TED.2016.2600625 | - |
| dc.identifier.scopusid | 2-s2.0-84983643616 | - |
| dc.identifier.wosid | 000384575700007 | - |
| dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.63, no.10, pp.3864 - 3868 | - |
| dc.relation.isPartOf | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
| dc.citation.title | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
| dc.citation.volume | 63 | - |
| dc.citation.number | 10 | - |
| dc.citation.startPage | 3864 | - |
| dc.citation.endPage | 3868 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Article | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalResearchArea | Physics | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
| dc.subject.keywordPlus | SOI MOSFETS | - |
| dc.subject.keywordPlus | DG MOSFETS | - |
| dc.subject.keywordAuthor | Compact modeling | - |
| dc.subject.keywordAuthor | double-gate (DG) MOSFETs | - |
| dc.subject.keywordAuthor | FinFETs | - |
| dc.subject.keywordAuthor | floating-body (FB) | - |
| dc.subject.keywordAuthor | parasitic bipolar junction transistor (BJT) | - |
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Related Researcher
- Seo, Sung kyu
- Department of Electronics and Information Engineering